1. Technical Field
The present invention relates to a semiconductor device having a field effect transistor (FET).
2. Related Art
Upon providing a cell shrinkage for a trench-based metal oxide semiconductor field effect transistor (MOSFET), the cell shrinkage is hampered due to dimensions of an edge of a side surface of the trench and a contact portion, and in order to solve the problem, a structure having an interlayer film embedded in the inside of the trench is proposed (see Japanese Patent Laid-Open No. 2002-373,988).
A configuration of a conventional device having an interlayer film embedded in the inside of a trench illustrated in “FIG. 1(a)” of Japanese Patent Laid-Open No. 2002-373,988 is roughly transcribed in FIG. 4. A trench-based MOSFET comprises a cell region having a trench structure, in which a gate electrode 5 is provided within a trench 11 via a gate oxide film 4 intervening therebetween, which is formed in a semiconductor layer 1 on a semiconductor substrate 1a. An insulating film 6 is provided on the gate electrode 5, and a source electrode 7 is provided on the insulating film 6. A source region 3 and a channel diffusion region 2 are formed on the side of the trench 11. Further, it is configured that a gate pad 5a is formed on a gate oxide film 4a within a trench 12 that is formed simultaneously with forming the trench 11 provided in the cell region, and that a circumference portion including the gate pad 5a surrounds the cell region.
However, in the technology described in Japanese Patent Laid-Open No. 2002-373,988, a depleted layer 16 extends through a portion under the trench 12 of the gate pad and beyond the circumference portion to the end of the chip, as shown in FIG. 5. Therefore, a leakage current may be generated from the transistor in the cell region through the depleted layer along the direction toward the end of the chip.
The present invention is made on the basis of such circumstances, and it is preferable to reduce the leakage current generated due to the extension of the depleted layer to the end of the chip.